The on-going demand for high performance electronic systems has driven the need for high-speed digital Very Large Scale Integration (VLSI) chips. VLSI implementations have proceeded in two inter-related directions: higher performance and higher density. As a general rule of thumb, higher performance requires more power. The growth in power consumption comes with a serious cost, including but not limited to: increased failure rates, expansive cooling systems, and decreased chip lifespan. Consequently, power consumption is a predominant challenge in improving modern high performance electronic systems.
Most of the modern VLSI designs are clocked. That is, the operations of logic gates within a VLSI chip are synchronized to act together according to clock signals. It is generally desired that clock signals between synchronized gates have low skew. Clock skew can be characterized as local skew and global skew. Local skew is the clock signal timing difference between logic gates that have timing paths between them within a single clock cycle. Global skew is defined as the clock signal timing difference between logic gates that have no timing paths between them in a single clock cycle.
As long as the gates can keep up within the limit of clock cycle time plus local skew, the higher the clock rate the higher the performance. Unfortunately, as VLSI chip densities increase, the foundry that produces these VLSI chips also introduces more variations into VLSI chips, which is known as the On-Chip Variation (OCV). Due to the OCV, the clock and data signals behave statistically, meaning that in one chip, the clock signal of cycle N happens in X pico-second, in another VLSI chip of same design and process, it can be (X+variation) pico-second. During the design process, a designer will need to add extra margins into VLSI chip designs to account for the OCV. So for a VLSI Clock Delivery Network (CDN), low skew and low OCV between clock delivery points become a high priority design goal. There are various methods for maintaining clock skew, one of which is a clock tree having leaf-level clock drivers spanning an entire mesh structure, with all of the leaf-level clock drivers connected (i.e., short) their outputs together. This mesh structure (on which all of the clock signals shorted together) is referred herein as a traditional clock mesh or traditional mesh. The leaf-level clock drivers are the clock delivery points to the gates receiving the clock signals.
A traditional mesh lowers local skew and OCV at the same time. By shorting the leaf-level clock drivers, a traditional mesh is able to average out the skew between these leaf-level clock drivers.
The leaf-level clock drivers in a traditional mesh drive an entire wire mesh and the registers underneath the mesh. The traditional mesh structure reduces individual driver variation; however, when clock meshes drive a large amount of loading, more individual drivers are needed in order to maintain the correct electronic property of clock transitions. As a result, short-circuit current between clock drivers goes up drastically. Short-circuit current occurs when a clock driver and its neighboring driver change state at different times. Since these clock drivers have their output connected to each other, when one driver's output pull up faster than its neighbor, the current will flow directly from this driver's output into its neighbor's output pins. If this driver's output pulls up slower than its neighbor, the short-circuit current goes the other way. Either way, a designer induces more short-circuit power consumption to lower the OCV.
Peak power consumption is sometimes a bigger issue than short-circuit power since modern VLSI can only support a limited amount of power while function correctly. Peak power of modern synchronous VLSI normally occurs when a maximum number of transistors switch within a short period of time. Since transistors switch right after their clock signal is activated, peak power is highly correlated to the global skew. With a tighter (i.e., smaller) global skew, there is a higher possibility of a larger total number of transistor switching together hence higher peak power consumption. Peak current density is a function of global skew.
Traditional clock delivery structures do not address OCV, clock skew, short-circuit power consumption and peak power consumption all at the same time. Thus, a circuit designer sometimes is forced to choose between higher full chip peak power consumption and higher clock speed.